The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further scaling down or micro-miniaturization of the physical dimensions of circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, resulting in several problems.
One such problem is stresses formed between copper through-silicon vias (TSVs) and silicon substrates as a result of the difference between the coefficients of thermal expansion (CTE) of copper and silicon. For example, copper has a CTE of 16.5; whereas silicon has a CTE of 2.6. This CTE mismatch may cause significant stress in the silicon and copper. As a result of the micro-miniaturization, when the TSVs are close together, the stress fields caused by the difference in CTE interact, further magnifying the stress. This stress causes numerous problems, including thin-film delamination, cracking, and the degradation of transistor performance over time.
A need therefore exists for methodology enabling formation of air gaps around TSVs, and the resulting device.